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| CY7C187 64K x 1 Static RAM Features * High speed -- 15 ns * CMOS for optimum speed/power * Low active power -- 495 mW * Low standby power -- 110 mW * TTL compatible inputs and outputs * Automatic power-down when deselected * Available in Pb-free and non Pb-free 22-pin (300-Mil) Molded DIP and 24-pin (300-Mil) Molded SOJ Functional Description The CY7C187 is a high-performance CMOS static RAM organized as 65,536 words x 1 bit. Easy memory expansion is provided by an active LOW Chip Enable (CE) and tri-state drivers. The CY7C187 has an automatic power-down feature, reducing the power consumption by 56% when deselected. Writing to the device is accomplished when the Chip Enable (CE) and Write Enable (WE) inputs are both LOW. Data on the input pin (DIN) is written into the memory location specified on the address pins (A0 through A15). Reading the device is accomplished by taking the Chip Enable (CE) LOW, while Write Enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified on the address pin will appear on the data output (DOUT) pin. The output pin stays in high-impedance state when Chip Enable (CE) is HIGH or Write Enable (WE) is LOW. The CY7C187 utilizes a die coat to insure alpha immunity. Logic Block Diagram Pin Configurations DI INPUT BUFFER A0 A1 A2 A3 A4 A5 NC A6 A7 DOUT WE GND SOJ Top View 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 C187-3 DIP Top View VCC A15 A14 A13 A12 NC A11 A10 A9 A8 DIN CE A12 A13 A14 A15 A0 A1 A2 A3 ROW DECODER 16K x 1 ARRAY SENSE AMPS DO A0 A1 A2 A3 A4 A5 A6 A7 DOUT WE GND CE COLUMN DECODER POWER DOWN 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 VCC A15 A14 A13 A12 A11 A10 A9 A8 DIN CE WE A4 A5 A6 A7 A8 A9 A10 A11 C187-1 C187-2 Selection Guide Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) -15 15 90 20 -25 25 70 20 -35 35 70 20 Cypress Semiconductor Corporation Document #: 38-05044 Rev. *A * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised July 24, 2006 [+] Feedback CY7C187 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential (Pin 22 to Pin 11) ........................................... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] ............................................ -0.5V to +7.0V DC Input Voltage[1] .........................................-0.5V to +7.0V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA Operating Range Range Commercial Ambient Temperature 0C to +70C VCC 5V 10% Electrical Characteristics Over the Operating Range -15 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., IOUT = 0 mA Max. VCC, CE VIH Max. VCC, CE VCC - 0.3V, VIN VCC - 0.3V or VIN 0.3V Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE PowerDown Current[3] Automatic CE Power-Down Current Test Conditions VCC = Min., IOH = -4.0mA VCC = Min., IOL =12.0 mA 2.2 -0.5 -5 -5 Min. 2.4 0.4 VCC 0.8 +5 +5 90 40 20 2.2 -0.5 -5 -5 Max. -25 and -35 Min. 2.4 0.4 VCC 0.8 +5 +5 70 20 20 Max. Unit V V V V A A mA mA mA Capacitance[4] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 10 10 Unit pF pF AC Test Loads and Waveforms R1 329 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 202 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 202 R1 329 ALL INPUT PULSES 3.0V GND 10% 90% 90% 10% 5 ns C187-5 5 ns (a) (b) C187-4 Equivalent to: THE VENIN EQUIVALENT 125 OUTPUT 1.90V Notes: 1. VIL (min.) = -3.0V for pulse durations less than 30 ns. 2. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 3. A pull-up resistor to VCC on the CE input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given. 4. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05044 Rev. *A Page 2 of 9 [+] Feedback CY7C187 Switching Characteristics Over the Operating Range[5] -15 Parameter READ CYCLE tRC tAA tOHA tACE tLZCE tHZCE tPU tPD WRITE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Output Hold from Address Change CE LOW to Data Valid CE LOW to Low Z [6] [6, 7] -25 Max. Min. 25 15 25 5 15 25 5 8 10 0 15 20 20 20 20 0 0 15 10 0 5 7 7 25 25 25 0 0 20 15 0 5 0 5 5 Max. Min. 35 -35 Max. Unit ns 35 35 15 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 ns Description Min. 15 3 3 0 CE HIGH to High Z CE LOW to Power Up CE HIGH to Power Down CYCLE[8] Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z[7] 15 12 12 0 0 12 10 0 5 Switching Waveforms Read Cycle No. 1[9, 10] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID C187-6 Notes: 5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device. 7. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 9. WE is HIGH for read cycle. 10. Device is continuously selected, CE = VIL. Document #: 38-05044 Rev. *A Page 3 of 9 [+] Feedback CY7C187 Switching Waveforms Read Cycle No. 2[9, 11] tRC CE tACE tLZCE DATA OUT HIGH IMPEDANCE DATA VALID tPD ICC 50% 50% ISB C187-7 tHZCE HIGH IMPEDANCE VCC SUPPLY CURRENT tPU Write Cycle No. 1(WE Controlled)[11] tWC ADDRESS tSCE CE tSA WE tSD DATA IN DATA VALID tHZWE DATA OUT DATA UNDEFINED C187-8 tAW tPWE tHA tHD tLZWE HIGH IMPEDANCE Note: 11. Address valid prior to or coincident with CE transition LOW. Document #: 38-05044 Rev. *A Page 4 of 9 [+] Feedback CY7C187 Switching Waveforms Write Cycle No. 2(CE Controlled)[11,13] tWC ADDRESS tSA CE tAW tPWE WE tSD DATA IN DATA VALID tHD tHA tSCE DATA OUT HIGH IMPEDANCE C187-9 Typical DC and AC Characteristics OUTPUT SOURCE CURRENT (mA) NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 NORMALIZED I CC, ISB 1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.0 4.5 5.0 ISB 5.5 6.0 I CC NORMALIZED I CC, I SB 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -55 ISB 25 125 VCC =5.0V VIN =5.0V I CC NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA =25C SUPPLY VOLTAGE(V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED t AA NORMALIZED t AA 1.3 1.2 1.1 TA =25C 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 1.6 1.4 1.2 1.0 AMBIENT TEMPERATURE (C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA =25C VCC =5.0V 0.8 0.6 -55 25 125 SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (C) OUTPUT SINK CURRENT (mA) OUTPUT VOLTAGE (V) Note: 12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Document #: 38-05044 Rev. *A Page 5 of 9 [+] Feedback CY7C187 Typical DC and AC Characteristics (Continued) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE NORMALIZED t AA (ns) 3.0 PO TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 NORMALIZED I CC 25.0 20.0 15.0 10.0 5.0 VCC =4.5V TA =25C 1.25 NORMALIZED I CC vs.CYCLE TIME VCC =5.0V TA =25C VCC =0.5V 1.00 2.5 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 NORMALIZED I 0.75 0.0 0 200 400 600 800 1000 0.50 10 20 30 40 SUPPLY VOLTAGE(V) CAPACITANCE (pF) CYCLE FREQUENCY (MHz) Address Designators Address Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 Address Function X3 X4 X5 X6 X7 Y7 Y6 Y2 Y3 Y1 Y0 Y4 Y5 X0 X1 X2 Pin Number 1 2 3 4 5 6 7 8 14 15 16 17 18 19 20 21 Truth Table CE H L L WE X H L High Z Data Out Data In Input/Output Deselect/Power-Down Read Write Mode Document #: 38-05044 Rev. *A Page 6 of 9 [+] Feedback CY7C187 Ordering Information Speed (ns) 15 25 Ordering Code CY7C187-15PXC CY7C187-25PC CY7C187-25VC CY7C187-25VXC 35 CY7C187-35VXC 51-85030 Package Diagram 51-85012 51-85012 51-85030 Package Type 22-pin (300-Mil) Molded DIP (Pb-free) 22-pin (300-Mil) Molded DIP 24-pin (300-Mil) Molded SOJ 24-pin (300-Mil) Molded SOJ (Pb-free) 24-pin (300-Mil) Molded SOJ (Pb-free) Commercial Operating Range Commercial Commercial Package Diagrams 22-pin (300-Mil) PDIP (51-85012) 11 1 DIMENSIONS IN INCHES MIN. MAX. 0.250 0.270 12 22 0.030 0.065 1.070 1.120 0.140 0.190 0.115 0.160 0.090 0.110 0.055 0.065 0.015 0.020 0.120 0.140 SEATING PLANE 0.280 0.325 0.015 0.060 0.009 0.012 0.310 0.385 3 MIN. 51-85012-*A Document #: 38-05044 Rev. *A Page 7 of 9 [+] Feedback CY7C187 Package Diagrams (Continued) 24-pin (300-mil) SOJ (51-85030) PIN 1 ID 12 1 DIMENSIONS IN INCHES[MM] REFERENCE JEDEC MO-088 0.291[7.39] 0.300[7.62] 0.330[8.38] 0.350[8.89] MIN. MAX. PACKAGE WEIGHT 0.75gms PART # 13 24 V24.3 VZ24.3 STANDARD PKG. LEAD FREE PKG. 0.597[15.16] 0.613[15.57] SEATING PLANE 0.120[3.05] 0.140[3.55] 0.004[0.10] 0.050[1.27] TYP. 0.025[0.63] MIN. 0.013[0.33] 0.019[0.48] 0.007[0.17] 0.013[0.33] 0.262[6.65] 0.272[6.91] 51-85030-*B All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05044 Rev. *A Page 8 of 9 (c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C187 Document History Page Document Title: CY7C187 64K x 1 Static RAM Document Number: 38-05044 REV. ** *A ECN NO. 107146 486744 Issue Date 09/10/01 See ECN Orig. of Change SZV NXR Description of Change Change from Spec number: 38-00038 to 38-05044 Removed 20 ns speed bin Changed Low standby power from 220mW to 110mW Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Updated the Ordering Information Table Document #: 38-05044 Rev. *A Page 9 of 9 [+] Feedback |
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